There was no PDP-8/V made by Digital. So I am making one myself, Out Of Electron Valves.

The plan is there will be approx 320 tubes, specifically 6J6A. As of May 24, 2023, there is one board completed, the sequencer that contains the state flip-flops plus an instruction register latch (just the top four bits), and all the instruction decoding logic. That board uses 80 tubes, which is 160 gates. The tubes just do the inverting, the logic is done by crystal rectifiers. It runs at 28k cps.

Each tube has 2 triodes. A single triode is required to make an AND-OR-INVERT gate. Three tubes (6 triodes) are required to make a D flipflop (ahem, edge-triggered, bi-stable multivibrator). Two tubes (4 triodes) are needed to make a latch.

The tubes are just the processor. For memory and I/O, I use a Raspberry PI. Transistors are used to do the level conversion between the RasPI and the tubes and to drive the LEDs. At some point, I might change the front panel to neons or incandescents with tube drivers, but LEDs will do for now.

When all the boards are done, it will run slower than 28k cps as there will be more circuitry for the bits to work their way through (27 levels of logic for the full processor as opposed to 10 for just the sequencer board). So that implies the processor will come in somewhere around 10k cps, though I wouldn't be surprised at 5k cps cuz of longer circuit traces.

As of June 4, 2023, the memory address register board is complete, adding 48 tubes. The whole thing clocks at 25.5k cps.

There are going to be a total of five tubulated boards, the sequencer (completed), the MA register (completed), the PC register, the AC/Link register, and the ALU (next up). There are also the backplane board and transistorized front panel board as shown below.

UPDATE as of November 12, 2023: THE WHOLE THING WORKS! See bottom of page.

Here is a video of just the sequencer and front panel running slowly (~5 cps) to see the lights blinking. The laptop is showing the RasPI output displaying the states. The FETCH-DEFER-EXEC-INTAK LEDs are stepping through the various states as the RasPI clocks the processor and sends it random opcodes. The top three bits of the instruction are shown in the IR LEDs. The RasPI checks the GPIO pins at the end of each cycle to make sure they are what they should be, as the RasPI knows what state the processor should be in for every cycle.

	sequencer board - 80 tubes - the crystal rectifiers are on the back
	sequencer board crystal rectifiers (and fan pointed at the tubes!)
	front panel - the whole thing is tipped on its side. RasPI is in bottom center of pic mounted to front panel board.
	8-tube board - the 80 tubes on the sequencer board are really 10 of these boards, all identical, each containing 16 generic inverters. They plug into the back of the large crystal rectifier board which gives them their individual personality. 32 more of these boards will have to be constructed, and plugged into the crystal rectifier boards, to complete the PDP-8/V.   Each 8-tube board requires +120V@45mA, -96V@35mA, +5V@10mA, 48V@400mA (8 6V filaments wired in series).   The allocation of the 8-tube boards to the crystal rectifier boards are: ACL (accum/link) - 8 x 8-tube boards ALU (arith/logic) - 9 x 8-tube boards MA (mem address) - 6 x 8-tube boards PC (prog counter) - 8 x 8-tube boards SEQ (state machine) - 10 x 8-tube boards
	the SEQ board with one of the 8-tube boards removed

When all said and done, I estimate it will use about a kilowatt of power total, about the same amount as a small space heater.

Here is another video, this one shows the processor running at 28k cps. Again, the RasPI verifies the GPIO pins at the end of each cycle to make sure it is working correctly. If I speed it up to 30k cps, the RasPI is quick to catch the errors.

Early on, there were the:

• 6J6 tube NAND gates Aug 18, 2022

• 6J6 tube D flipflop Aug 20, 2022

You may also be interested in the Hode retro-computing project.

	8-tube board section
	Making an and-or-invert gate with crystal rectifiers and an 8-tube board section
	D-flipflop from 6 NAND gates (diagram from Wikipedia) whenever Clock is low, B and C are high regardless of Data input, leaving E/F SR-FF output steady Data being low for setup time lets it soak into A making A high, then that soaks into D making D low (cuz C is being held high by the low Clock) then when Clock goes high, A is high, D is low, B goes low, driving E high and F low D stays low, C stays high if Data goes high (after being low for hold time after Clock) with Clock still high, B is still low, so A stays high, so nothing changes Data being high for setup time lets it soak into A making A low (cuz B is held high by the low clock), then that soaks into D making D high then when Clock goes high, B stays high (cuz A is low), C goes low (cuz D is high), driving F high and E low if Data goes low (after being high for hold time after Clock) with Clock still high, A goes high, B and D stay high cuz C is still low, so nothing changes Setup time would be however long it takes for the A B C D gates to stabilize after a Data change with Clock staying low. So Data has to soak (1) all the way through A, (2) into B's input and all the way through D, (3) into C's input. Hold time would be however long it takes for the A B C D gates to block changes in Data after Clock goes high. So Clock has to soak (1) all the way through B or C, (2) B soaks into A's input or C soaks into B's and D's input. Best I can tell is the design came from TI's 7474 datasheet, may have existed prior to that.

STATES

• = is for combinational computation, result available sometime during the current cycle
• ← is for loading D-flipflop-style register at end of cycle, new contents available near beginning of next cycle. The IR is actually a latch to save a couple tubes, but gets loaded by the end of the cycle so is similar to using D-flipflops.
• There is exactly one state per clock cycle, starting at rising edge of one clock and ending at the next rising edge
• Signals RasPI.IOInst,IntAck,MemRead,MemWrite come from the tubes and go to the RasPI. They are valid by the end of the clock cycle so the RasPI can read them just before driving the clock high for the next cycle. When not specifically mentioned, they are zero.
• Signals RasPI.IntReq,IOSkip come from the RasPI and go to the tubes. They are valid in the middle of the cycle through to the middle of the next cycle so they have plenty of time to soak into the tubes before getting clocked in and hold steady a bit after clocking.
• Signals RasPI.Data,Link are bi-directional under control of the RasPI. When in Tubes-To-RasPI mode, the values are valid by the end of the cycle, and RasPI.Data is always driven by the output of the ALU and RasPI.Link is always driven by contents of the Link register. When in RasPI-To-Tubes mode, they are valid in the middle of the cycle through to the middle of the next cycle.
• DEFER3 only happens for auto-incrementing locations
• The 3 state TAD only happens when AC is initially non-zero. Otherwise, it pretends it is an AND instruction with AC=7777 so it only takes two cycles as an optimization for common TAD following DCA. A full cycle is needed for adding via the ALU, only a half cycle is needed for anding.
• Group2 with OSR and/or HLT, and all Group3, are treated as an IOT, ie, punted to the RasPI.
• The final state of JMP (EXEC1), JMS (EXEC3) and Group2 (EXEC1), serves as a FETCH1 cycle if there is no interrupt being requested by the RasPI as an optimization.
• A read takes 2 cycles: (1) tubes send address to RasPI along with READ; (2) RasPI sends value to tubes
• A write takes 2 cycles: (1) tubes send address to RasPI along with WRITE; (2) tubes send value to RasPI
• A read/modify/write takes 3 cycles: (1) tubes send address to RasPI along with READ and WRITE; (2) RasPI sends original value to tubes; (3) tubes send modified value to RasPI
• An IO takes 2 cycles: (1) tubes send Link,AC to RasPI along with IOInst; (2) RasPI sends IOSkip,Link,AC to tubes. The opcode was present on the data bus just prior to the cycle with IOInst.

GPIO BUS - The GPIO Bus connects the processor to the Raspberry PI via the RasPI GPIO connector. Direction is from perspective of RasPI.

    Block diagram:

            ma  --------------------------------------------------------------+
            mq          ac  ----------------------------------------------+   |
            pc          +1                                                |   |
            -1          -1                                                |   |
             0           0                                                |   |
        +---------------------+                                           |   |
        |    A           B    |                                           |   |
        |         ALU         |                                           |   |
        |          Q          |                                           |   |
        +---------------------+                                           |   |
                   |                                                      |   |
                   +----------------------- rotator -------   AC,LINK  ---+   |
                   |                                                          |
                   +---------------------------------------   MA       -------+
                   |                                                          |
                   +---------------------------------------   PC       -------+
                   |                                                          |
                   +---------------------------------------   RasPI    -------+------  IR/SEQ

ALU functions:

• ALU_ADD = perform addition ALUA + ALUB
• ALU_AND = perform bitwise and ALUA & ALUB
• GRPA1 = perform group 1 arithmetic according to opcode in MA register
• INC_AXB = compute (A ^ B) + 1

Backplane signals:

Note:

• bits are numbered 11 = MSB, 00 = LSB
• 'MQ' refers to memory contents coming from raspberry pi
• signals beginning with _ are active low, all others active high
• the rotator is part of the AC/LINK board
• the IR is part of the SEQ board, and only stores bits 11,10,09,08
  - the MA is used for the lower opcode bits for the group 1,2 instructions
• clok2 comes from raspberry pi
  • each board internally inverts it exactly twice before going to flipflops
  • after the first inversion, it is called _clok1
  • after the second inversion, it is called clok0
  • only clok0 signals are allowed to clock flipflops for consistent timing

Update as of May 28, 2023

	front panel standing up video standing up
	+120V power supply with 80 tubes plugged in
	other power supplies with 80 tubes plugged in the filament power supply is on the left with the big capacitor on a piggy-back circuit board to soft-start the filaments

Update as of June 4, 2023

	sequencer and memory address boards total of 80 + 48 = 128 tubes! video of MA register countdown test program
	power supplies with sequencer and memory address boards the -96V supply shows 96.06V 536mA 51.48W (from above pic)
	running test program at 25+k cps short video

Update as of June 7, 2023 - ALU board ordered

Update as of June 20, 2023 - Well, the whole thing ran with the ALU board for about 10 minutes (at 16k cps)! Then things started going nuts, so the honeymoon is over!

I'm going to make some paddles for unit testing the boards, similar to the Hode paddles . The chips can only handle -0.5V to +5.5V so the new paddles will need Schottkys for clamping. The big tube boards have 4 32-pin single-row connectors so the new paddles will have to be designed for all that. They can plug into the USB ports of a RasPI or a Linux PC that will run test programs to find problems.

Anyway, the 16k cps is encouraging as there are only a couple more layers of logic around the longest path (27 vs 25). So theoretically, the final processor should run somewhere near that, hoping for 10k or better at this point.

Update as of July 4, 2023 - Stupid paddles , the IOWarriors have internal pullups and so load the tubes down too much. So I have designed new paddles with 2N7000 buffers, hopefully they will work. That's about $200 down the twaletty.

Update as of July 18, 2023 - Got the new paddles working and testing the ALU board. The paddles are very slow but what the heck they run. I have some new IOWarrior-100 chips on order hopefully will speed it up.

tube side of ALU board with new paddles		crystal rectifier side of ALU board with new paddles
short video running test program

The test program shown in the video simulates all the boards and provides inputs required to the ALU board via the paddles (highlighted in blue on the screen). At the end of each cycle, the test program reads all the outputs from the ALU board (highlighted in red) via the paddles and checks to make sure they are correct. It generates random instructions for the simulator to generate the test cases. I also have a test program that directly generates random numbers to feed to the ALU for testing. Both programs show the ALU is working.

There are a bunch of test clips you might notice on the tube side. Turns out a digitally keyed parts supplier sent me a bunch of 3.6V zener diodes when I had ordered 3.0V zeners. They were marked by the manufacturer as 3.0V (we looked at them under the microscope and they showed 3V0B), so it isn't the supplier's fault. Those clips go to a couple resistors to fudge the cathode bias down from 3.6V to 3.0V. At any rate, it seems to work equally well with 3.0V, 3.3V and 3.6V so I'm going to leave those zeners in unless they cause problems (the output voltages from the tubes would be a little higher with 3.6V for cathode bias instead of 3.0V). Measuring a heavily loaded point, the zero is well negative (-3V) coming out of the voltage divider with the cathode at 3.6V, so that's plenty good enough. I should do some more measurements (now that I have a couple hundred test cases) before building new boards to decide which zeners to use going forward.

Update as of August 20, 2023 - Have all constructed boards working with paddles, SEQ, MA, ALU, RPI.

• blinking lights in dark
• blinking lights in light
• test program driving the boards

The last video shows the test program. Red stuff is output from the boards onto the busses such as ALUQ, MAQ. Blue stuff is signals being generated by the paddles, such as AC, PC cuz I don't have the AC and PC boards yet. Also at the bottom in blue are signals being output by the GPIO pins such as CLOCK, IRQ (interrupt request). The DATA line alternates red and blue because it is bi-directional for the data being sent between the RasPI and the tubes.

I have physically re-arranged things because I bought an infrared camera. It showed some of the resistors on the tube boards were running at 180..190°F and the max they are rated for is 160°F (70°C). Now I have a fan basically for each board and now the resistors run around 120°F max. So I'm going to have to re-think the backplane to make room for more cooling for the last two boards (PC and AC/Link).

Update as of October 27, 2023

• new backplane with more spacing between the boards
• put the thing in a wire rack to make it easier to place fans
• have 4 fans instead of just 2
• added ACL board (accumulator and link registers). all that remains to be built is the PC (Program Counter) board.
• it reached the point of needing a dedicated electrical circuit. it now draws 11.5A @ 120VAC = 1380VA.

Video with RPI, SEQ, MA, ALU, ACL boards in place - total of 264 tubes so far.

• on the left side (blinking lights panel):
  1. RPI board - 0 tubes - raspberry pi and blinking lights
  2. SEQ board - 80 tubes - sequencer
  3. MA board - 48 tubes - memory address register
• on the right side (big white fan):
  1. ALU board - 72 tubes - arithmetic logic unit
  2. ACL board - 64 tubes - accumulator and link registers

• The values in red are generated by the tubes and sent to the raspberry pi
• The values in blue are generated by the raspberry pi and sent to the tubes
• The last 3 lines (starting with JUMP, DATA, CLOCK) are the memory/IO bus going between the tubes and the raspberry pi gpio connector
  • the first of the 3 lines are bits coming from the tubes going to the pi (eg, wanting to READ or WRITE memory)
  • the DATA line is sometimes blue (reading memory, io register), sometimes red (writing memory, io register)
  • the third line is where the test program generates the signals in blue sends them to the tubes (CLOCK, RESET, etc)
• All the other lines are on the backplane (the raspberry pi accesses them via the paddles plugged into the backplane on the right rear)
  • the test program generates the missing PC bits (in blue) and sends them to the backplane via the paddles
  • the test program validates all the other backplane signals (in red) at the end of each cycle
  When the PC board is complete, the PCQ line will be red, indicating that the test program is verifying the PC register output at the end of each cycle.

Update as of October 28, 2023

• I updated the test program that runs without paddles. It assumes the outputs from missing boards are ones and steps it through its cycles at whatever speed I want. Seems the tubes are happy running (with a missing PC register board) at just over 14 kcps. Since the slowest thing is the ALU doing an addition of some sort, the PC register board shouldn't slow it down, so I think it is realistic to think the final processor, with the PC register board in place, will run around 12-14 kcps.

Update as of November 12, 2023

IT WORKS! YEAY!

All boards are put together and tested (at least for a couple hours). It clocks at 13+ kcps. It runs OS/8 using an emulated RK05.

• video of the blinking lights and some of the tubes
• pic of some tube boards (SEQ on left, ALU, ACL on right)
• pic of some more tubes in back (backside of ACL on left with paddles, tubeside of PC on right)
• Uses 5 20-inch attic fans
• Must be careful to get the voltages just right, +120.0, -96.0, +5.0. A couple tenths either way is OK, but a volt or two on the high voltages causes it to crap out.
• Power usage: 15.7A @ 113V, 1.72 KW, PF 0.97